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Altium designer 17 measure distance free.Interactively Routing with Controlled Impedances on a PCB in Altium Designer
MeasureDistance | Altium Designer User Manual | Documentation
During PCB fabrication the surface of copper layers are treated to increase the roughness, to improve the adhesion between the copper and dielectric layers. Through extensive research and analysis, industry experts have concluded that the surface roughness can be modeled by a roughness correction coefficient, derived from Surface Roughness and Roughness Factor values.
Roughness settings are available in the Layer Stack Manager mode of the Properties panel. These parameters are used only for conductive layers. Surface roughness is included in the calculation of the characteristic impedance. The impedance calculator in the Layer Stack Manager supports single and differential coplanar structures. The impedance calculator determines the signal properties and clearances first image , use that clearance in the via shielding Distance setting.
In a controlled impedance design, the selection of the materials used in the layer stackup is very important. For example, the most common material used to fabricate PCBs is glass fiber fiberglass reinforced epoxy resin, with copper foil bonded onto each side.
The tightness of the weave of the glass fiber fabric affects the value and consistency of the dielectric constant Dk permittivity and Loss Tangent Df. Surrounding the woven glass fabric is resin - the percentage of resin used is also important in the performance of the material. There is a large range of glass fiber weaves available.
To help ensure the predictability and performance of the glass fiber-based materials used in PCB fabrication, the IPC have a standard for weaves:. As the designer, you can either edit the material properties directly in the Layer Stack Manager , or select materials from the Altium Material Library. The materials are organized into usage categories, accessed through a tree structure on the left of the dialog.
Below this level, each usage category is broken into functional categories, such as: Conductive layer material , Dielectric layer material and Surface Layer Material ; in the PCB layer material category. New material can added to the library when a specific material category is selected in the tree. Materials defined in an external material library can be loaded Load button , and user-defined material that has been added in the Altium Material Library dialog can also be saved to a user-library Save button.
Only user-defined material is saved. Custom properties can be added to material detailed in the library default and user-defined material. To add a custom property, first select the correct node in the tree on the left to define the material s it is to be added to, then click the button to open the Material Library Settings dialog. The required value can then be added to the selected material in the Altium Material Library dialog, select the row and click the Edit button. The dispersion over frequency can be described with a multi-pole Debye model - which requires multiple frequency points to build.
When the Impedance tab of the Layer Stack document is active, the Properties panel allows you to configure the Impedance Profile requirements.
The routing impedance is determined by the width and height of the route, and the properties of the surrounding dielectric materials. Based on the material properties defined in the Layer Stack Manager , the required routing widths are calculated when each impedance profile is created. Depending on the material properties, the width may change as the routing layer is changed. This requirement changes widths as you change routing layers is automatically managed by the applicable routing design rule configured in the PCB Rules and Constraints Editor Design » Rules.
For most board designs, there will be a specific set of nets to be routed with a controlled impedance. A common approach is to create a net class or differential pair class that includes these nets, then create a routing rule that targets this class, as shown in the images below. Normally you manually define the Min , Max , and Preferred Widths , either in the upper constraint settings to apply them to all layers; or individually for each layer in the layer grid.
For controlled impedance routing you enable the Use Impedance Profile option instead, then select the required Impedance Profile from the dropdown. When this is done, the Constraints region of the rule will change. The first thing you will notice is that the available layers region will no longer show all signal layers on the board, it will now only show the layers enabled in the selected Impedance Profile.
The Preferred Width values and diff pair gap will update to reflect the widths and gaps calculated for each layer. The nets can then be interactively routed, in the usual way.
For single-sided nets, the routing width is defined by the Routing Width design rule. When you choose to Use an Impedance Profile, the available layers and Preferred Widths are controlled by the selected profile. The routing of differential pairs is controlled by the Differential Pair Routing design rule. For a differential pair, the available layers, the Preferred Width and the Preferred Gap are controlled by the selected profile. Breaks or necks in the return path can be detected by the Return Path design rule.
The Return Path design rule checks for a continuous signal return path on the designated reference layer s above or below the signal s targeted by the rule. The return path can be created from fills, regions, and polygon pours placed on the reference signal layer, or it can be a plane layer. The return path layers are the reference layers defined in the Impedance Profile selected in the Return Path design rule.
These layers are checked to ensure the specified Minimum Gap width beyond the signal edge exists along the signal's path. Add a new Return Path design rule in the High Speed rule category. The return path layers are defined in the selected Impedance Profile , the path width beyond the signal edge is defined by the Minimum Gap.
The image below shows return path errors detected for the signal, NetX , with a Minimum Gap setting of 0. Doing this highlights the exact locations where the rule has failed rather than the entire object s in violation. To avoid detecting small errors, such as the section highlighted in the diagonal track segment in the image above, configure the PCB. As you route the board and change layers, the software will automatically adjust the track width to the size needed to achieve the specified impedance.
This interactive controlled impedance routing greatly simplifies the task of designing a controlled impedance PCB. For a surface mount pad, set the Layer to Top Layer. For a thru-hole pad, set the Layer to Multi-Layer. Additional Designator and Comment strings can be included by placing the. Designator and. Comment special strings on a mechanical layer.
Based on the formulae developed for the IPC standard, the Wizard generates the footprint using standard Altium Designer objects, such as pads and tracks. This Wizard allows you to select from various package types and fill in appropriate information and it will then build the component footprint for you. Note that in the Footprint Wizard you enter the sizes required for the pads and component overlay.
Some footprints require pads that have an irregular shape. This can be done using any of the design objects available in the PCB Library Editor, but when doing this, there is an important factor that must be kept in mind. Create irregular shaped pads by placing multiple objects. Altium Designer automatically adds solder and paste masks to pad objects based on their shape. Default expansion values are defined by design rules by default, although they can also be specified by the Pad settings contained on the PCB Editor - Defaults page of the Preferences dialog.
These settings can be overridden during placement or after placement through the Properties panel. Main article: Working with Custom Pad Shapes. If only pad objects have been used to build up an irregular shape, the matching irregular mask shape will automatically be generated as an expansion of the pad shape.
But if the irregular shape was built up using other objects, such as lines tracks , fills, regions, pads, vias, or arcs, the solder and paste masks will need to be configured manually. All object-kinds have a solder mask property, and fill and region objects also have a paste mask expansion property. If these objects have been placed on the top layer to create a pad shape, then the solder mask property of those objects can be enabled to either obey the applicable design rule, or use a manual expansion value.
If fill and region objects have been used to build up a pad shape, then the paste mask can also be enabled as a property of the extra objects.
When the mask shape is not correctly created as an expansion or contraction of the set of objects used to create the custom pad shape, then manually defined solder and paste mask expansions can be also achieved by placing lines tracks , fills, regions, or arc primitives directly on the corresponding solder or paste mask layer. The custom button footprint shown below is an example of this. The ring that appears around the edge of each pad in the color of the Top Solder Mask layer represents the edge of the solder mask shape protruding by the expansion amount from under the multi-layer pad because multi-layer is at the top of the layer drawing order; it is drawn on top.
The image below shows a PCB footprint with a purple color of the Top Solder Mask layer border that appears around the edge of each pad. The footprint shown below is the contact set for a push button switch implemented directly in the copper on the surface layer of the PCB. Printed push button footprint designed by placing pads, lines and arcs.
A rubber switchpad overlay is placed on the PCB, with a small captive carbon button that contacts both sets of fingers in the footprint when the button is pressed to create the electrical connectivity. For this to happen, both sets of fingers must not be covered by the solder mask.
The circular solder mask opening has been achieved by placing an arc whose width is equal to or greater than the arc radius, resulting in the solid purple circle shown behind the two sets of fingers. Each set of copper fingers has been defined by an arc, horizontal lines, and a pad selected in the image to make them visible. The pads are required to define the points of connectivity.
Manually placed top solder mask definitions are automatically be transferred to the bottom side solder mask layer if the component is placed on the bottom side of the board.
A common approach to defining custom shapes on the mask layers is to build up the shape on the Solder Mask or Paste Mask layer from standard objects. These objects can include pads, which designers sometimes choose to achieve a rounded rectangle shape they require on the solder paste layer.
In this situation, the required shape can be created from a Region object. Rather than drawing the region object, it can sometimes be simpler to define the outline of the shape from line and arc objects, and then convert that shape to a region object, as demonstrated below.
The required rounded rectangle shape is created by tracing a pad with lines and arcs, and then converting the shape formed by the lines and arcs, to a region object. Parameters applied to objects in Altium Designer provide a powerful and flexible means of adding additional information to a PCB design.
Applied as properties of the parent object, parameters can be applied at a range of levels, including projects, documents, templates, and individual objects within a design document. This is a one-way transfer and the passed parameters are read-only in the PCB domain. When the ECO is executed by using the Execute Changes button , any new user-defined schematic component parameters will be transferred to the corresponding footprint reference in the PCB design.
To view the transferred parameters in the PCB editor, double-click a component to open the Properties panel then choose the Parameters tab. The tab will list the current user parameters that have been assigned to the selected component footprint. Parameters for a selected component footprint also are available in the Components panel. These are defined as parameter pairs Description and link URL that normally establish data reference links to specific files or internet locations — typically a manufacturer web site or datasheet URL.
In both the schematic and PCB design space, the links are accessed from the right-click context menu when hovering over a component under the References sub-menu options.
The specialized parameters are added in the Properties panel, and when transferred to the PCB space, they appear as a component footprint parameter. Parameters passed to the PCB can be used for providing additional board production or functional information via component footprints.
By adding special parameter strings to footprints at the source library level, the custom strings will be interpreted on the target mechanical layer or overlay. A special string representing a user-defined parameter can be added to the source component footprint using the special strings button and drop-down in the Properties panel. In the below library footprint, the special string. Designator has been placed on the Mechanical 2 layer. A special string representing a user parameter can be added to the component footprint.
When that custom parameter has also been applied to schematic components and the parameter data has been transferred to the PCB, the interpreted footprint strings will appear on both the board view and generated output files.
In this case the special parameter string contains a custom component part identifier to aid assembly. The application of the user parameters to component footprints as special strings can serve a range of other custom PCB requirements, including function labels for switches and connectors, where a 'function' parameter string might be placed on the Top Overlay in footprints for those component types.
Parameter strings in the PCB domain are also accessible through the Altium Designer query language, and therefore, are available for object filtering functions, including the Find Similar Objects feature.
Align selected design objects by their top edges while maintaining adequate spacing in observance with applicable design rules. Align selected design objects by their bottom edges while maintaining adequate spacing in observance with applicable design rules. Viewing the Board. Switch the display of the PCB design space to 2D Layout Mode and see the same location and orientation of the board as you switch.
Switch the display of the PCB design space to 3D Layout Mode and see the same location and orientation of the board as you switch. Flip the active board, or active component, just as if you were turning it over in your hand.
Zoom-in, relative to the current cursor location. You can also use the mouse to zoom in to a region of the document by one of the following methods where applicable and depending on how the buttons of your mouse might be assigned : Hold the Ctrl key and roll the mouse wheel upward.
Use of the Ctrl key is a default setting that can be changed from the System - Mouse Wheel Configuration page of the Preferences dialog. Hold both the Ctrl key and the right mouse button, then move the mouse forward. Hold the right first and left second mouse buttons, then move the mouse forward. Click and hold the mouse wheel, then move the mouse forward. Zoom-out, relative to the current cursor location. You can use the mouse to zoom out from a region of the document by one of the following methods where applicable and depending on how the buttons of your mouse might be assigned : Hold the Ctrl key and roll the mouse wheel downward.
Hold both the Ctrl key and the right-mouse button, then move the mouse backward. Hold the right first and left second mouse buttons, then move the mouse backward. Click and hold the mouse wheel, then move the mouse backward. Scroll vertically within the design space. This is a default setting that can be changed from the System - Mouse Wheel Configuration page of the Preferences dialog.
Scroll horizontally within the design space. Redraw the view in the main design window, placing the location marked by the cursor - prior to launching the command - at the center of the window.
Refresh the screen, in effect performing a redraw of the current document, to remove any undesirable drawing update effects. Redraw the current layer of the current document, to remove any undesirable drawing update effects. Access the Layers And Colors tab of the View Configuration panel in which you can configure the display of layers for the board and the colors assigned to those layers. Access the View Options tab of the View Configuration panel in which you can configure the mode used to display each of the various design items within the design space.
Board Insight Display. Access the Board Insight pop-up, listing all violations of defined Design Rules currently under the cursor. Access a pop-up window in which to define which objects to be used for snapping purposes.
The choices made are reflected back in the Snap Options region of the Properties panel on the General tab when viewing options for a PCB document. Set the X horizontal and Y vertical step values - for the default Global Board Snap Grid - simultaneously to a chosen value. Once enabled, the cursor will pull or snap to the nearest snap group location. Viewing Differences Legacy Collaborative Design. Toggle the state of the current cell containing detected differences between checked and unchecked when using Altium Designer's Collaborative PCB Design functionality where a comparison has been performed from the Collaborate, Compare and Merge panel.
Navigate to the previous cell containing one or more detected differences when using Altium Designer's Collaborative PCB Design functionality where a comparison has been performed from the Collaborate, Compare and Merge panel. Navigate to the next cell containing one or more detected differences when using Altium Designer's Collaborative PCB Design functionality where a comparison has been performed from the Collaborate, Compare and Merge panel.
On a net object to highlight the entire routed net. On a layer tab to highlight all content on that layer. In free space to clear current highlighting.
On a net object to highlight the entire routed net in addition to the routed nets already highlighted cumulative routed net highlighting. On a layer tab to highlight all content on that layer in addition to the content already highlighted on other layers cumulative layer highlighting.
Increase the masking level, which decreases the extent of dimming in the design space for all objects not falling under the scope of the currently applied filter.
Note that this shortcut is only effective when the highlighting method for objects not passing the applied filter is set to Dim. Unlike the Mask highlighting method, such objects can still be selected and edited.
Decrease the masking level, which increases the extent of dimming in the design space for all objects not falling under the scope of the currently applied filter.
Quick Panel Access. Layer Switching. Use Glossing to improve the quality of the selected routes by reducing the overall length and number of corners. Add a new comment thread to a point, object, or area on the active PCB document. Before you can start using the comment feature, ensure that you have opened checked out a Managed Project and are working on its PCB document.
Move the cursor to the relative origin of the current document PCB document , or the location of the component reference point PCB Footprint document. In the main design space to access the Selection Memory dialog , from where you can control all aspects of the selection memory feature. In a dialog or panel to toggle the measurement units in the dialog or panel only , between metric mm and imperial mil. To make it easy to identify important nets in the design, you can add Net Labels to assign names.
For the multivibrator circuit, you will label the 12V and GND nets in the circuit, as shown below. The net label in free space left image and positioned over a wire right image , note the red cross. You have just completed your first schematic capture.
Before you turn the schematic into a circuit board you need to configure the project options, and check the design for errors. The project options include the error checking parameters, a connectivity matrix, Class Generator, the Comparator setup, ECO generation, output paths and connectivity options, Multi-Channel naming formats, Default Print setups, Search Paths, and project-level Parameters.
These settings are used when you compile the project. Project outputs, such as assembly, fabrication outputs and reports can be set up from the File and Reports menus. These settings are also stored in the Project file so they are always available for this project. An alternate approach is to use an OutputJob file to configure the outputs, with the advantage that an OutputJob can be copied from one project to the next.
See More About Outputs to learn more configuring the outputs. After you complete the schematic in Altium Designer, you compile it. This generates an internal connectivity map of the design, detailing all of the components and nets.
When the project is compiled, comprehensive design and electrical rules are also applied to verify the design. When all errors are resolved, the compiled schematic design is ready to be transferred to the target PCB document by generating a series of Engineering Change Orders ECOs. Underlying this process is a comparator engine that identifies every difference between the schematic design and the PCB, and generates an ECO to resolve each difference. This approach of using a comparator engine to identify differences means you not only work directly between the schematic and PCB there is no intermediate netlist file used , it also means the same approach can be used to synchronize the schematic and PCB at any stage during the design process.
The comparator engine also allows you to find differences between source and target files and update synchronize in both directions. Refer to the Design Synchronization page to learn more. Schematic diagrams are more than just simple drawings - they contain electrical connectivity information about the circuit. You can use this connectivity awareness to verify your design. When you compile a project, the software checks for errors according to the rules set up in the Error Reporting and Connection Matrix tabs of the Options for Project dialog.
When you compile the project any violations that are detected will display in the Messages panel. Dialog page: Error Reporting. The Error Reporting tab in the Options for Project dialog is used to set up a large range of drafting and component configuration checks. The Report Mode settings show the level of severity of a violation. If you wish to change a setting, click on a Report Mode next to the violation you wish to change and choose the level of severity from the drop-down list.
Configure the Error Reporting tab to detect for design errors when the project is compiled. Dialog page: Connection Matrix. When the design is compiled a list of the pins in each net is built in memory. The type of each pin is detected eg: input, output, passive, etc , and then each net is checked to see if there are pin types that should not be connected to each other, for example an output pin connected to another output pin.
The Connection Matrix tab of the Options for Project dialog is where you configure what pin types are allowed to connect to each other. For example, look down the entries on the right side of the matrix diagram and find Output Pin. Read across this row of the matrix till you get to the Open Collector Pin column.
The square where they intersect is orange, indicating that an Output Pin connected to an Open Collector Pin on your schematic will generate an error condition when the project is compiled. You can set each error type with a separate error level, eg. Click on a colored square to change the setting, continue to click to move to the next check-level. Set the matrix so that Unconnected Passive Pin generates Error , as shown in the image below.
The Connection Matrix defines what electrical conditions are checked for on the schematic, note that the Unconnected - Passive Pin setting is being changed. Dialog page: Class Generation. The Class Generation tab in the Options for Project dialog is used to configure what type of classes are generated from the design the Comparator and ECO Generation tabs are then used to control if classes are transferred to the PCB.
By default, the software will generate Component classes and Rooms for each schematic sheet, and Net Classes for each bus in the design.
For a simple, single-sheet design such as this there is no need to generate a component class or a room - ensure that the Component Classes checkbox is cleared, doing this will also disable the creation of a room for that component class. Note that this tab of the dialog also includes options for User-Defined Classes. The Class Generation tab is used to configure what classes and rooms are automatically created for the design.
Dialog page: Comparator. The Comparator tab in the Options for Project dialog sets which differences between files will be reported or ignored when a project is compiled. Generally the only time you will need to change settings in this tab is when you add extra detail to the PCB, such as design rules, and do not want those settings removed during design synchronization. If you need more detailed control, then you can selectively control the comparator using the individual comparison settings.
For this tutorial it is sufficient to confirm that the Ignore Rules Defined in PCB Only option is enabled, as shown in the image below. The Comparator tab is used to configure exactly what differences the comparison engine will check for.
Main article: Compiling and Verifying the Design. Compiling a project checks for drafting and electrical rules errors in the design documents, and details all warnings and errors in the Messages panel. You have set up the rules in the Error Checking and Connection Matrix tabs of the Options for Project dialog, so are now ready to check the design.
The blank PCB has been added to the project. Add a new PCB to your project. Main article: The Board. There are a number of attributes of this blank board that need to be changed before transferring the design from the schematic editor, including:. Select the command, position the cursor over the lower-left corner of the board shape left image , then click to define the origin right image.
For this design, it is more efficient to edit the existing board shape. These commands are only available in Board Planning Mode. The resize cursor is shown, use the location information on the Status bar to help you resize the board to 30mm x 30mm.
The board size has been defined, and the units, origin and grid have been set. The required layers will be configured shortly. A good approach to defining the shape of a non-rectangular board is to place a series of tracks and arcs for curved boards on the keepout layer. As well as being useful as a placement and routing keep-away barrier, these tracks and arcs can be selected Edit » Select » All on Layer and used to create the board shape using the Design » Board Shape » Define from Selected Objects command.
Main article: Working Between the Schematic and the Board. The design is transferred directly between the schematic editor and the PCB editor, there is no intermediate netlist file created. When you run either of these commands the design is compiled and a set of Engineering Change Orders is created, which:.
Once the ECOs have been executed, the components are placed outside the board shape and the nets are created.
Note that the default Designator and Comment fonts have been changed. Before transferring the schematic information to the new blank PCB, make sure all the related libraries for both schematic and PCB are available. Since only the Altium Content Vault is used in this tutorial, the required Vault is already available.
As the Vault includes the symbol and the footprint, then the footprints required for the tutorial are also available. For example, if you want the component designators for all of your PCB designs to be 1. Once all of the ECOs have been executed the components and nets will appear in the PCB workspace, just to the right of the board outline, as shown in the image above. Before you start positioning the components on the board you need to configure certain PCB workspace and board settings, such as the layers, grids and design rules.
Panel page: View Configuration. As well as the the layers used to fabricate the board, including: signal, power plane, mask and silkscreen layers, the PCB Editor also supports numerous other non-electrical layers. The layers are often grouped in the following way:. The display attributes of all layers are configured in the View Configuration panel. To open the panel:. The two tabs of the View Configuration panel.
As well as the layer display state and color settings, the View Configuration panel also gives access to other display settings, including:. Dialog page: Layer Stack Manager. As well as the signal and power plane solid copper layers, the PCB Editor also includes soldermask and silkscreen physical layers - these are all used during the fabrication of the physical board.
The arrangement of these layers is referred to as the Layer Stack. The tutorial PCB is a simple design and can be routed as a single-sided or double-sided board. The layer thicknesses shown below have been edited to use sensible metric values. The properties of the physical layers are defined in the Layer Stack Manager. To edit a cell either: double-click in the cell; or select the cell and press F2 to show the dropdown or edit the value.
The next step is to select a grid that is suitable for placing and routing the components. All the objects placed in the PCB workspace are placed on the current snap grid. Traditionally, the grid was selected to suit the component pin pitch and the routing technology that you planned to use for the board - that is, how wide do the tracks need to be, and what clearance is needed between tracks.
The basic idea is to have both the tracks and clearances as wide as possible, to lower the fabriction costs and improve the reliability. Over time, components and their pins have dramatically shrunk in size, as has the spacing of their pins.
The component dimensions and the spacing of their pins has moved from being predominantly imperial with thru-hole pins, to being more-often metric dimensions with surface mount pins.
If you are starting out a new board design, unless there is a strong reason, such as designing a replacement board to fit into an existing imperial product, you are better off working in metric.
Because the older, imperial components have big pins with lots of room between them. Also, the PCB editor can easily handle routing to off-grid pins, so working with imperial components on a metric board is not onerous. For a design such as this simple tutorial circuit, practical grid and design rule settings would be:. While it might be tempting to select a very fine routing grid so that routing can effectively be placed anywhere, this is not a good approach.
Select View » Toggle Units or press the Q shortcut key to toggle the workspace units between metric and imperial. Regardless of the current setting for the units, you can include the units when entering a value in a dialog or panel to force that value to be used. Altium Designer allows multiple snap grids to be defined. As well as defining the type of grid, you can also define the area where that grid applies. Note that the Default grid always applies to the entire workspace, even though it is only displayed over the board shape.
Since only one grid can be used at a time, grids also have a priority which is used to determine which grid should be applied when they overlap. There are also controls for defining if a grid is for all objects, components only, or non-components only. Grids are created and managed in the Grid Manager section of the Properties panel.
Use the buttons in the panel to add, edit or delete a grid. Multiple grids can be configured in the Grid Manager , an image of these 3 grids is shown on the right click to enlarge. Set the Snap Grid to 1 mm, ready to position the components. The PCB Editor is a rules-driven environment, meaning that as you perform actions that change the design, such as placing tracks, moving components, or autorouting the board, the software monitors each action and checks to see if the design still complies with the design rules.
If it does not, then the error is immediately highlighted as a violation. Setting up the design rules before you start working on the board allows you to remain focused on the task of designing, confident in the knowledge that any design errors will immediately be flagged for your attention. The rules are divided into 10 categories, which can then be further divided into design rule types.
Design rule reference: Width. The width of the routing is controlled by the applicable routing width design rule, which the software automatically selects when you run the Interactive Routing command and click on a net. When you are configuring the rules, the basic approach is to set the lowest priority rule to target the largest number of nets, and then add higher-priority rules to target nets with special width requirements, such as power nets.
There is no issue if a net is targeted by multiple rules, the software always looks for and only applies the highest priority rule. For example, the tutorial design includes a number of signal nets, and two power nets. The default routing width rule can be configured at 0. This rule will target all nets in the design by setting the rule scope to All. The image below shows the summary of these two rules, the detail is shown in the images in the following two collapsible sections.
Two Routing Width design rules have been defined, the lowest priority rule targets All nets, the higher priority rule targets objects in the 12V net or the GND net. Use these if you prefer to have some flexibility during routing, for example when you need to neck a route down, or use a smaller via in a tight area of the board. Note that you always remain constrained by the design rules, if you enter a value larger or smaller than permitted by the applicable design rule it will be clipped to the nearest rule value.
Avoid using the Min and Max settings to define a single rule to suit all sizes required in the entire design, doing this means you forgo the ability to get the software to monitor that each design object is appropriately sized for its task. The default Routing Width design rule has been configured. This Width rule targets the power nets.
When there are multiple rules of the same type, the PCB editor uses the rule Priority to ensure the highest priority applicable rule is applied. Design rule reference: Clearance Constraint. The next step is to define how close electrical objects that belong to different nets, can be to each other.
This requirement is handled by the Electrical Clearance Constraint, for the tutorial a clearance of 0. Note that entering a value into the Minimum Clearance field will automatically apply that value to all of the fields in the grid region at the bottom of the dialog. You only need to edit in the grid region when you need to define a clearance based on the object-type.
The electrical clearance constraint is defined between objects. Switch the Constraints to Advanced to display all object kinds. Design rule reference: Routing Via Style. As you route and change layers a via is automatically added, in this situation the via properties are defined by the applicable Routing Via Style design rule.
If you place a via from the Place menu, its values are defined by the in-built default primitive settings. For the tutorial, you will configure the Routing Via Style design rule.
A single routing via is suitable for all nets in this design. You might have noticed that the transistor pads are showing that there is a violation. Right-click over a violation and select the Violations in the right-click menu, as shown below. The details show that there is a:.
Right-click on a violation to examine what rule is being violated, and the violation conditions. In this image the display is in single layer mode, with the Top Layer as the active layer. This violation will be discussed and resolved shortly.
If you find the violation markers distracting, you can clear them by running the Tools » Reset Error Markers command. This command only clears the marker, it does not hide or remove the actual error.
The error will be flagged again the next time you perform an edit action that runs the online DRC such as moving the component , or when you run the batch DRC. The default new board created by the software will include rules that are not needed in every design, and many other design rules will need to be adjusted to suit the requirements of your design.
For this reason, it is very important to review the design rules. This can be done in the PCB Rules and Constraints Editor , select Design Rules at the top of the tree on the left, then you can scan down the Attributes column for all of the rules and quickly locate any that need their values adjusted.
The default board also uses imperial units, if your board uses metric then there will be many rule values, such as the Soldermask expansion, that will change from rounded values like 4mil, to 0. While that least significant digit, for example 0. Reviewing the design rules, note the column order can be changed if required. When you create a new board, it will include default design rules that might not be needed for your design.
For example, Assembly and Fabrication Testpoint type design rules are included when you create a new board, which are not needed in this design. Design rules can also be exported and stored in a. Select the rules you wish to export using the standard Windows selection techniques, then click OK to export the selected rules. While you could argue about the percentage of each, it is generally accepted that good component placement is critical for good board design.
Keep in mind that you may need to tune the placement as you route too. When you click and hold on a component to move it, if the Snap to Center option is on, then the component will move to be held by its reference point. The reference point is the 0,0 coordinate of the component, when it was built in the library editor. The Smart Component Snap option allows you to override this snap to center behavior and snap to the nearest component pad instead, handy when you need to position a specific pad in a specific location.
Enable Snap to Center to always hold the component by its reference point. Smart Component Snap is helpful when you need to align by a specific pad.
Components positioned on the board. Select, then align and space the resistors. Selected objects can also be moved using the keyboard rather than the mouse. To do this, hold Ctrl , then each time you press an Arrow key the selection will move 1 grid step in the direction of that arrow. Include the Shift key to move selected objects in 10x Snap Grid steps.
When you are moving a component with the mouse, you can constrain it to an axis by holding the Alt key. The component will attempt to hold the same horizontal axis if moving horizontally or vertical axis if moving vertically - move it further from the axis to override this behavior, or release the Alt key.
Main article: Interactive Routing. Routing is the process of laying tracks and vias on the board to connect the component pins. The PCB editor makes this job easy by providing sophisticated interactive routing tools, as well as ActiveRoute, which optimally routes selected connections with the click of a button. In this section of the tutorial, you will manually route the entire board single-sided, with all tracks on the top layer. The Interactive Routing tools help maximize routing efficiency and flexibility in an intuitive way, including cursor guidance for track placement, single-click routing of the connection, pushing obstacles, automatically following existing connections, all in accordance with applicable design rules.
Configure the interactive routing options. Set the Snap Grid to a value that is suitable for routing. A simple animation showing the board being routed. Note how the segments are displayed differently. Keep an eye on the Status bar , it displays important information during interactive routing, including:. The PCB editor's Interactive Routing engine supports a number of different modes, with each mode helping the designer deal with particular situations.
To modify an existing route, there are two approaches, either: reroute , or re-arrange. A simple animation showing the Loop Removal feature being used to modify existing routing. Note that there are situations where you may want to create loops, for example power net routing. If necessary, Loop Removal can be disabled for an individual net by editing that net in the PCB panel. To access the option set the panel to Nets mode, then double click on the net name in the panel to open the Edit Net dialog.
During Loop Removal, you will find situations where you return to the existing routing, but are not yet finished defining the new path. When the Automatically Terminate Routing option is enabled, as soon as the new route overlays the existing route, the routing process will terminate and the old, redundant routing will be removed. In this situation it can be more efficient to disable the Automatically Terminate Routing option.
An animation showing track dragging being used to tidy up existing routing. An example of dragging multiple tracks, by setting the routing conflict mode to Push.
Main article: ActiveRoute. Another approach to routing the nets on your board is to use ActiveRoute, Altium's automated interactive router. What does that mean?
It means you select the connection or connections to route, choose the layer, and run ActiveRoute. ActiveRoute has efficient multi-net routing algorithms, these are applied to the specific nets or connections that you have selected. ActiveRoute also allows the designer to interactively define a route path or Guide, which then defines the river along which the new routes will flow.
ActiveRoute has been developed for dense boards using high pin count components, to help accelerate what can be a difficult and time-consuming routing process. This board is not the sort of board it was designed for, but it provides an opportunity to demonstrate and explore its use.
The tutorial board, ready to be used to explore ActiveRoute. The ActiveRoute results. The PCB editor is a rules-driven board design environment, in which you can define many types of design rules that can be checked to ensure the integrity of your board. Typically you set up the design rules at the start of the design process.
The on-line DRC feature will monitor the enabled rules as you work and immediately highlight any detected design violations. Alternatively, you can also run a batch DRC, to test that the design complies with the rules, generating a report that details the enabled rules and any detected violations.
Earlier in the tutorial you examined the routing design rules, adding a new width constraint rule targeting the power nets, as well as an electrical clearance constraint and a routing via style rule.
As well as these, there are a number of other design rules that are automatically defined when a new board is created. Altium Designer has two techniques for displaying design rule violations, each with their own advantages. Violations can be displayed as a colored overlay and also as a detailed message, with different symbols being used to show different detail of the error type.
Violations are shown in solid green left image , as you zoom in this changes to the selected Violation Overlay Style center image , as you zoom in further Violation Details are added. The rules that are needed will depend on the nature of your design, there is no specific set of rules that suits every design.
Keep this in mind as you are checking rule violations, ask yourself, do I need this rule to be enabled? If you're attempting to work out the function of a rule in the PCB Rules and Constraints Editor and are unsure, click anywhere in the constraints area of the rule and press F1 for more information about that specific rule.
Dialog page: Design Rule Checker. The design is checked for violations by running the Design Rule Checker. Run the Tools » Design Rule Check command to open the dialog. Both online and batch DRC are configured in this dialog.
Rule checking, both online and batch, is configured in the Design Rule Checker dialog. Checking is configured for each rule type, use the right-click menu to enable the Used design rules. Click the Run Design Rule Check button at the bottom of the dialog to perform a design rule check. When the button is clicked the DRC will run, then:. The upper section in the report details the rules that are enabled for checking and the number of detected violations, click on a rule to jump down the report and examine those errors.
The lower section of the report shows each rule that is being violated, followed by a list of the objects in error.
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